Evaluation of Test Strategies in Vhdl Descriptions: a Case Study

Current design processes are based on top down methodologies, using hardware description languages as the input of the design flow. This trend motivates changes in the test generation and fault simulation processes in order to establish an efficient method to evaluate test strategies at high abstraction levels. To make this possible it is necessary to adopt a fault model compatible with the circuit or system description. Several fault models at behavioral or Register Transfer (RT) level have been reported by many authors in the recent last past years. These models are used to estimate, at high abstraction levels, the structural fault coverage obtainable with a specific test strategy. A fault model at RT level is proposed in [1], for VHDL (VHSIC Hardware Description Language) descriptions. This fault model is based on single and permanent faults, divided in three classes: faults on data, on expressions and faults on statements. The development of a fault model and a fault injection algorithm are both described in [2], considering that a RT level fault list is a representative sample of the corresponding collapsed gate-level list. Taken from software testing, a fault model named single bit stuck-at fault is presented in [3]. The authors propose a single-bit stuck-at in an assignment operation at RT level and assume single fault injection with permanent effects. The correlation at gate level is obtained experimentally. However, there is no a clear relationship between structural faults and RT or behavioral faults. In this work, we present preliminary results obtained from the evaluation at RT Level of a previously reported test strategy [4]. Both a RTL fault model and a fault injection procedure are adopted in order to obtain the RT level fault coverage that can be later compared with a structuralfault one. 2. TEST STRATEGY